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HM 65664A
8 K 8 Very Low Power CMOS SRAM
Introduction
The HM 65664A is a very low power CMOS static RAM organized as 8192 x 8 bit. It is manufactured using the TEMIC high performance CMOS technology named super CMOS. With this process, TEMIC is the first to bring the solution for applications where fast computing is as mandatory as low consumption, such as aerospace electronics or portable instruments and PC's. Using an array or six transistors (6T) memory cells, the HM 65664A combines an extremely low standby supply current (typical value = 0.1 A) with a fast access time at 25 ns over the full temperature range. The high stability of the 6T cell provides with excellent protection against soft errors due to noise. Extra protection against heavy ions is given by the use of an epitaxial layer on a P substrate. For military/space applications that demand superior levels of performance and reliability the HM 65664A is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D Access Time Industrial/Commercial : 25/35/45/55 ns (max) Automotive/Military : 30/35/45/55 ns (max) D Very Low Power Consumption Active : 175.0 mW (Typ) Standby : 0.5 W (Typ) Data Retention : 0.4 W (Typ) D Wide Temperature Range : -55 To + 125C D D D D D D 300 and 600 Mils Width Packages TTL Compatible Inputs and Outputs Asynchronous Single 5 Volt Supply Equal Cycle and Access Time Gated Inputs : No Pull-up/Down Resistors Are Required
MATRA MHS Rev. C (11 Apr. 97)
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HM 65664A
Interface
Block Diagram
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MATRA MHS Rev. C (11 Apr. 97)
HM 65664A
Pin Configuration
Plastic 300 & 600 mils, 28 pins, DIL. Ceramic 300 & 600 mils, 28 pins, DIL. SOIC & SOJ 300 mils, 28 pins SOIC 330 mils, 28 pins LCC, 32 pins.
Pinout DIL/SOJ 28 pins (top view)
Pinout LCC 32 pins (top view)
Logic Symbol
Pin Names
A0-A12: Address inputs I/O0-I/O7 VCC GND : Input/Outputs : Power : Ground CS1 CS2 OE W : Chip-select 1 : Chip-select 2 : Output Enable : Write enable
CS1 CS2 OE
H L L L X H H H X L X H
W
X H L H
DATA- IN
Z Z Valid Z
DATA- OUT
Z Valid Z Z
MODE
Deselect Read Write Output disable
L = low, H = high, X = H or L, Z = High impedance
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . -0.5 V to +7.0 V Input or Output voltage applied : . . . . (Gnd - 0.3 V) to (Vcc + 0.3 V) Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Electro Static Discharge voltage > 2000 V (MILSTD 883C method 3015.2)
Operating Range
OPERATING VOLTAGE
Military Automotive Industrial Commercial (- 2) (- A) (- 9) (- 5) VCC 10 % VCC 10 % VCC 10 % VCC 10 %
OPERATING TEMPERATURE
- 55_C to + 125_C - 40_C to + ??? - 40_C to + 85_C 0_C to + 70_C
MATRA MHS Rev. C (11 Apr. 97)
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HM 65664A
Recommended DC Operating Conditions
PARAMETER
VCC GND VIL VIH Note : (1)
DESCRIPTION
Supply Voltage Ground Input low voltage Input high voltage
MINIMUM
4.5 0.0 - 0.3 2.2
TYPICAL
5.0 0.0 0.0 -
MAXIMUM
5.5 0.0 0.8 Vcc + 0.3 V
UNIT
V V V V
1. VIL min = -0.3 V or -1.0 V pulse width 50 ns.
Capacitance
PARAMETER
Cin Cout Note : (2) (2)
DESCRIPTION
Input capacitance Output capacitance
MINIMUM
- -
TYPICAL
- -
MAXIMUM
8 8
UNIT
pF pF
2. TA = 25C, f = 1 MHz, VCC = 5.0 V, these parameters are not tested.
DC Parameters
PARAMETER
IIX IOZ VOL VOH Note : (3) (4) (4) (3)
DESCRIPTION
Input leakage current Output leakage current Output low voltage Output high voltage
MINIMUM
- 1.0 - 1.0 - 2.4
TYPICAL
- - - -
MAXIMUM
1.0 1.0 0.4 -
UNIT
A A V V
3. Gnd < Vin < Vcc, Gnd < Vout < Vcc, output disabled, CS1 2.2 V or CS2 0.8 V. 4. Vcc min, IOL = 4.0 mA, IOH = -1.0 mA.
Consumption for Commercial Specification (-5)
SYMBOL
ICCSB (5) ICCSB1 (6) ICCOP (8) Notes :
PARAMETER
Standby supply current Standby supply current Operating supply current
65664A 65664A 65664A 65664A 65664A 65664A 65664A 65664A U-5 T-5 G-5 Q-5 B-5 S-5 -5 C-5
10 1 70 15 75 80 10 1 65 15 75 75 10 1 65 15 75 75 10 1 65 15 75 75
UNIT
mA A mA
VALUE
max max max
5. CS1 VIH and CS2 VIL. 6. CS1 Vcc - 0.3 V and CS2 0.3 V, Iout = 0 mA. 7. Vcc max, Iout = 0 mA, f = max, Vin = Gnd/Vcc.
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MATRA MHS Rev. C (11 Apr. 97)
HM 65664A
Consumption for Industrial Specification (-9)
SYMBOL
ICCSB (5) ICCSB1 (6) ICCOP (8)
PARAMETER
Standby supply current Standby supply current Operating supply current
65664A 65664A 65664A 65664A 65664A 65664A 65664A 65664A U-9 T-9 G-9 Q-9 B-9 S-9 -9 C-9
15 5 75 20 100 100 15 5 75 20 100 100 15 5 75 20 100 100 15 5 75 20 100 100
UNIT
mA A mA
VALUE
max max max
Consumption for Automotive (-A) and Military (-2) Specifications
SYMBOL
ICCSB (5) ICCSB1 (6) ICCOP(7) Notes :
PARAMETER
Standby supply current Standby supply current Operating supply current
65664A G-2
15 50 75
65664A Q-2
20 500 100
65664A B-2
15 50 75
65664A S-2
20 500 100
65664A -2
15 50 75
65664A C-2
20 500 100
UNIT
mA A mA
VALUE
max max max
5. CS1 VIH and CS2 VIL. 6. CS1 Vcc - 0.3 V and CS2 0.3 V, Iout = 0 mA. 7. Vcc max, Iout = 0 mA, f = max, Vin = Gnd/Vcc.
AC Parameters AC Conditions
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output load : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL gate + 30 pF
AC Test Loads and Waveforms
Figure 1 a
Figure 1 b
Figure 2
MATRA MHS Rev. C (11 Apr. 97)
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HM 65664A
Data Retention Mode
MHS CMOS RAM's are designed with battery backup applications in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention : 1. Chip select (CS) must be held high during data retention ; within Vcc to Vcc -0.2 V 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 2. CS and OE must be kept between Vcc -0.3 V and 70 % of Vcc during the power up and power down transitions 3. The RAM can begin operation > 45 ns after Vcc reaches the minimum operating voltage (4.5 V).
Timing
Data Retention Characteristics
PARAMETER
VCCDR TCDR TR ICCDR1(11)
DESCRIPTION
Vcc for data retention Chip deselect to data retention time Operation recovery time Data retention current @2.0 V : HM-65664AB/G/U-5 HM-65664AB/G/U-9 HM-65664AB/G-2/-A HM-65664AS/C/Q/T-5 HM-65664AS/C/Q/T-9 HM-65664AS/C/Q-2/-A Data retention current @2.0 V : HM-65664AB/G/U-5 HM-65664AB/G/U-9 HM-65664AB/G-2/-A HM-65664AS/C/Q/T-5 HM-65664AS/C/Q/T-9 HM-65664AS/C/Q-2/-A
MINIMUM TYPICAL (9) MAXIMUM
2.0 0.0 TAVAV (10) - - - - - - - - - - - - - - - 0.1 0.1 0.1 0.1 0.1 0.1 0.3 0.3 0.3 0.3 0.3 0.3 - - - 0.5 3.0 20.0 30.0 30.0 200.0 1.0 5.0 30.0 50.0 50.0 300.0
UNIT
V ns ns A A A A A A A A A A A A
ICCDR2(11)
Notes :
9. TA = 25C. 10. TAVAV = Read cycle time. 11. CS = Vcc, Vin = Gnd/Vcc, this parameter is only tested to Vcc = 2 V.
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MATRA MHS Rev. C (11 Apr. 97)
HM 65664A
Write Cycle : Commercial Specification
SYMBOL TAVAV TAVWL TAVWH TDVWH TEL1WH TEH2WH TWLQZ (12) TWLWH TWHAX TWHDX TWHQX (12) PARAMETER Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 low to write end Write low to high Z Write pulse width Address hold to end of write Data hold time Write high to low Z 65664A 65664A 65664A 65664A 65664A 65664A 65664A 65664A U-5 T-5 G-5 Q-5 B-5 S-5 -5 C-5 25 0 25 20 25 25 15 25 5 3 0 25 0 25 20 25 25 15 25 5 3 0 35 0 35 22 35 35 15 30 5 3 0 35 0 35 22 35 35 15 30 5 3 0 45 0 45 25 45 45 15 40 5 3 0 45 0 45 25 45 45 15 40 5 3 0 55 0 55 25 55 55 20 50 5 3 0 55 0 55 25 55 55 20 50 5 3 0 UNIT ns ns ns ns ns ns ns ns ns ns ns VALUE min min min min min min max min min min min
Write Cycle : Industrial, Automotive and Military Specifications
SYMBOL TAVAV TAVWL TAVWH TDVWH TEL1WH TEH2WH TWLQZ (12) TWLWH TWHAX TWHDX TWHQX(12) Note : PARAMETER Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 low to write end Write low to high Z Write pulse width Address hold to end of write Data hold time Write high to low Z 65664A 65664A 65664A 65664A 65664A 65664A 65664A 65664A G-9/-2 Q-9/-2 B-9/-2 S-9/-2 -9/-2 C-9/-2 U-9 T-9 /-A /-A /-A /-A /-A /-A 30 0 30 22 30 30 15 27 5 3 0 30 0 30 22 30 30 15 27 5 3 0 35 0 35 22 35 35 15 30 5 3 0 35 0 35 22 35 35 15 30 5 3 0 45 0 45 25 45 45 15 40 5 3 0 45 0 45 25 45 45 15 40 5 3 0 55 0 55 25 55 55 20 50 5 3 0 55 0 55 25 55 55 20 50 5 3 0 UNIT ns ns ns ns ns ns ns ns ns ns ns VALUE min min min min min min max min min min min
12. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
MATRA MHS Rev. C (11 Apr. 97)
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HM 65664A
Write Cycle 1 W Controlled (note 13)
Write Cycle 2 CS 1 Controlled (note 13)
Note :
13. The internal write time of the memory is defined by the overlap of CS LOW and W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
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MATRA MHS Rev. C (11 Apr. 97)
HM 65664A
Read Cycle : Commercial Specification
SYMBOL TAVAV TAVQV TAVQX TEL1QV TEH2QV TEL1QX TEH2QX TEH1QZ TEL2QZ TGLQV TGLQX TGhQZ PARAMETER Read cycle time Address access time Address Valid to low Z Chip-select 1 access time Chip-select 2 access time CS1 low to low Z CS2 to low Z CS1 high to high Z CS2 low to high Z Output Enable access time OE low to low Z OE high to high Z 65664A 65664A 65664A 65664A 65664A 65664A 65664A 65664A U-5 T-5 G-5 Q-5 B-5 S-5 -5 C-5 25 25 3 25 25 5 5 25 25 12 5 15 25 25 3 25 25 5 5 25 25 12 5 15 35 35 3 35 35 5 5 35 35 15 5 15 35 35 3 35 35 5 5 35 35 15 5 15 45 45 3 45 45 5 5 45 45 15 5 15 45 45 3 45 45 5 5 45 45 15 5 15 55 55 3 55 55 5 5 55 55 20 5 20 55 55 3 55 55 5 5 55 55 20 5 20 UNIT ns ns ns ns ns ns ns ns ns ns ns ns VALUE min max min max max min min max max max min max
Read Cycle : Industrial, Automotive and Military Specifications
SYMBOL TAVAV TAVQV TAVQX TEL1QV TEH2QV TEL1QX TEH2QX TEH1QZ TEL2QZ TGLQV TGLQX TGHQZ PARAMETER Read cycle time Address access time Address Valid to low Z Chip-select 1 access time Chip-select 2 access time CS1 low to low Z CS2 to low Z CS1 high to high Z CS2 low to high Z Output Enable access time OE low to low Z OE high to high Z 65664A 65664A 65664A 65664A 65664A 65664A 65664A 65664A U-9 T-9 G-9/2/A Q-9/2/A B-9/2/A S-9/2/A -9/2/A C-9/2/A 30 30 3 30 30 5 5 30 30 15 5 15 30 30 3 30 30 5 5 30 30 15 5 15 35 35 3 35 35 5 5 35 35 15 5 15 35 35 3 35 35 5 5 35 35 15 5 15 45 45 3 45 45 5 5 45 45 15 5 15 45 45 3 45 45 5 5 45 45 15 5 15 55 55 3 55 55 5 5 55 55 20 5 20 55 55 3 55 55 5 5 55 55 20 5 20 UNIT ns ns ns ns ns ns ns ns ns ns ns ns VALUE min max min max max min min max max max min max
MATRA MHS Rev. C (11 Apr. 97)
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HM 65664A
Read Cycle nb 1 (notes 16, 17)
Read Cycle nb 2 (notes 16, 18)
Notes : 16. W is high for read cycle. 17. Device is continuously selected, CS1 & OE = VIL AND CS2 = VIH. 18. Address valid prior to or coincident with CS transition low.
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MATRA MHS Rev. C (11 Apr. 97)
HM 65664A
Burn-in Schematics
VCC = 5 V (-0, + 0.5) R = 1 K per pin FO = 50 KHz 20%
Fn = 1/2 Fn - 1 SO to S3 : programmable signals for write/read cycles NC : Not Connected
MATRA MHS Rev. C (11 Apr. 97)
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HM 65664A
Ordering Information
PACKAGE HM U DEVICE TYPE 65664A GRADE B LEVEL -5 : R
0 - Chip form 8 k x 8 Ultimate CMOS 1 - Ceramic 28 pins static RAM 300 mils 1E - Ceramic 28 pins 600 mils 3 - Plastic 28 pins 300 mils B = high speed/low current 3E - Plastic 28 pins S = high speed/standard current 600 mils Blank : standard speed/low current 4 - LCC 32 pins C : standard T- SOIC 300 mils 28 pins Q = Very high speed/standard current TP- SOIC 330 mils 28 pins G = Very high speed/low current U - SOJ 28 pins U = 25 ns/low current (*) 300 mils T = 25 ns/standard current (*) C = Side brazed 28 pins 300 mils (*) for commercial, 30 ns for other levels CE = Side brazed 28 pins 600 mils D = Flat pack 28 pins 400 mils
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX :R : RD :D
= = = = = = = = = = = =
MHS standards MIL STD 883 Class B or S MIL STD 883 + PIND test SCC 9000 level B/C Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape and reel Tape and reel dry pack Dry pack
Military and Space Versions
The following table gives package/consumption/access time/process flow available combinations
Temp. range Packages
G 35 50 M 1 1E 4 D 0 C CE 4 D 0 D D D X X D D D X X
Access Time (ns) Iccsb (A)
Q 35 500 D D D X X B 45 50 D D D X X D D D X X S 45 500 D D D X X C 55 500 D D D X D
Std process 65664A
Mil flows
RT process 65664F
Mil flows Space flows ( including SCC9301029)
55 50 D D D X X D D D X X
D D D X D D D D X D D D D X D
S
X
D
D = product in production X = call sales office for availibility
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
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MATRA MHS Rev. C (11 Apr. 97)

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